1. Field of the Invention
This invention relates to a static random access memory (which is hereinafter referred to as an SRAM) and is utilized for a semiconductor integrated circuit device having an SRAM mounted thereon, for example.
2. Description of the Related Art
In recent years, various problems appear in the SRAM with an increase in the memory capacity and a lowering in the voltage. The prior art of the SRAM and the problem associated therewith are explained below with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram of a memory cell (which is hereinafter referred to as an SRAM cell) used to configure a conventional 6-transistor SRAM. The conventional SRAM cell has first and second inverters I1, 12 which are cross coupled and respectively connected to complementary paired bit lines BL, /BL via first and second transfer gate transistors T1 and T2. The first, second inverters I1, 12 are respectively configured by first, second driver transistors D1, D2 and first, second load transistors L1, L2 (for example, refer to FIG. 2 in Jpn. Pat. Appln. KOKAI Publication No. 2000-58675). In this case, the transfer gate transistors T1 and T2, driver transistors D1, D2 and load transistors L1, L2 are designed to have the same gate length (L), the same gate width (W) and the same threshold voltage (Vth).
At the read time, cell data is read out to the bit line pair by activating the word line WL to drive one of the paired bit lines BL and /BL to the “L” potential side by use of a cell current Ic. Further, at the write time, data is written into a memory cell by activating the word line WL to bias the paired bit lines BL, /BL to desired data polarities.
FIG. 2 shows a bistable characteristic (butterfly curve) indicating the data storage stability in the conventional SRAM cell. The curve indicates the transfer curve (VNB-VNA static characteristic) of the first inverter I1 obtained by respectively plotting VNB, VNA on the abscissa and ordinate and the transfer curve of the second inverter I2 obtained by respectively plotting VNA, VNB on the abscissa and ordinate where VNA, VNB indicate storage node potentials of the SRAM cell shown in FIG. 1.
At this time, the word line WL and bit line pair BL, /BL are biased to power supply voltage VDD. In FIG. 2, the state in which the SRAM cell holds “1” data, that is, the node potential VNA is set at “H” and the node potential VNB is set at “L” corresponds to an intersection XB of the above two transfer curves and the state in which the SRAM cell holds “0” data corresponds to an intersection XA.
The length of one side of maximum squares which respectively internally touch two regions surrounded by the two transfer curves is defined as a static noise margin (SNM). Generally, the stability of data stored in the SRAM cell becomes higher and data destruction due to power supply voltage noise in the chip becomes more difficult to occur as the static noise margin becomes larger. Therefore, it becomes important to set a large static noise margin when designing the SRAM cell.
Further, the X coordinate of a point A at which the transfer curve starts to drop from the power supply voltage VDD is set to threshold voltage Vthn of the driver transistor D1. As is clearly understood from FIG. 2, the static noise margin can be enlarged by enhancing the threshold voltage Vthn of the driver transistor D1. In this case, however, if the threshold voltage Vthn is enhanced, the cell current Ic is reduced and the operation speed is lowered.
Thus, in the conventional case, an attempt to enhance the stability (increase SNM) of data storage in the SRAM cell and setting a larger cell current are set in a trade-off relation when the threshold voltage of the driver transistor is set. In recent years, as the SRAM cell is miniaturized and the driving voltage becomes lower, the problems that the set window of the threshold voltage of the driver transistor which simultaneously satisfies the above two conditions becomes narrower and the cell designing becomes difficult occur.